Advancements in PLL and VCO Technologies

A CDTA-based quadrature oscillator circuit is proposed. The circuit employs two current-mode allpass sections in a loop, and provides high-frequency sinusoidal oscillations in quadrature at high impedance output terminals of the CDTAs. The circuit has no floating capacitors, which is advantageous from the integrated c…

• ALİ ÜMİT KESKİN

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• ALİ ÜMİT KESKİN

Phase noise and timing jitter in oscillators and phase-locked loops (PLLs) are of major concern in wireless and optical communications. In this paper, a unified analysis of the relationships between time-domain jitter and various spectral characterizations of phase noise is first presented. Several notions of phase no…

• ALPER DEMİR

This paper presents 64-quadrature amplitude modulation (QAM) 60-GHz CMOS transceivers with four-channel bonding capability, which can be categorized into a one-stream transceiver and a two-stream frequency-interleaved (FI) transceiver. The transceivers are both fabricated in a standard 65-nm CMOS technology. For the p…

A fractional-N sub-sampling PLL architecture based on pipelined phase-interpolator and Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined phase-interpolator and DTC enables efficient design of the multi-phase generation mechanism required for the fractional operation. This techniq…

A new circuit configuration uses a single operational transresistance amplifier (OTRA) and four passive elements to realize both first- and second-order allpass filters. Owing to internal grounding of the OTRA input terminals, effects of input parasitics are significantly reduced. Applications of the circuit include t…

Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterisation. In t…

Attenuators are analyzed for their minimum Insertion Loss (IL), maximum attenuation and source-load matching performance. These results are used to make trade-offs in the design of a CMOS attenuator with wide dynamic range, designed and fabricated in a 0.13$\mu{\hbox{m}}$CMOS process. The design employs two non-identi…

• HAKAN DOĞAN

This paper presents a 60-GHz CMOS transceiver targeting the IEEE 802.11ay standard. A calibration block for local oscillator feedthrough (LOFT) and I/Q imbalance featuring high accuracy and low power consumption is integrated with the transceiver. With the help of the proposed calibration, this paper is capable of boo…

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• MEHMET OĞUZHAN ÇİÇEKOĞLU

Abstract In this paper a mixed‐mode (input and output signals can be current or voltage) Kerwin–Huelsman–Newcomb (KHN) biquad with low/high input impedance and high/low output impedance depending on the type of the corresponding signal (current/voltage) is presented. The circuit is constructed using three differential…

• ŞAHRAM MİNAYİ

This paper presents behavioral simulation techniques for phase/delay-locked systems. Numerical simulation algorithms are compared and the issue of numerical noise is discussed. Behavioral phase noise simulation for phase/delay-locked systems is described. The role of behavioral simulation for phase/delay-locked system…